Interface Circuit

ABSTRACT

An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive-feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

TECHNICAL FIELD

The present invention relates to an interface circuit that is applied tovarious kinds of electronic devices and stabilizes an electrical stateof external input/output terminals.

BACKGROUND ART

In general, a signal transmitted by a device in a digital systembasically has two states aside from a floating state. The first state isdesigned to transmit a phenomenon corresponding to a logic high level(also called “logic high”, “High”, “1”, “ON” or “H level”). The secondstate is designed to transmit a phenomenon corresponding to a logic lowlevel (also called “logic low”, “Low”, “0”, “OFF” or “L level”).

A particular signal potential that determines which of a logic highsignal and a logic low signal is being transmitted depends upon asemiconductor device that forms a circuit related to the transmission.

For example, the most common circuit configurations used to produce adigital signal include a CMOS logic IC and a transistor-transistor logic(TTL) IC. In the CMOS logic IC, the logic low signal generally falls ina range of from a potential applied to a low-voltage terminal to apotential that is about 0.6 V higher than that applied to thelow-voltage terminal, whereas the logic high signal is generally set ina range of from Vcc to Vcc-0.6 V if a potential applied to ahigh-voltage terminal is Vcc. As it is a well-known technical matterthat a relationship between a signal potential and a logic level isdetermined depending on a device, this technical matter will not bespecifically described below.

All sorts of data processing systems functioning as digital systems areusually provided with a plurality of external input terminals (aconnector) for signal input. A plurality of input terminals (pins) forsignal input are provided to a semiconductor integrated circuit such asa CPU which is installed in a data processing system. Sometimes acontrol terminal for switching operation modes of a CPU or the like isfurther provided to the semiconductor integrated circuit. The externalinput terminal has a function as an interface that inputs a logic signalhaving an H or L level, which is given from an external device, totransmit the signal to an internal circuit, such as a CPU and a memory.The control terminal has a function to switch the control information tobe given to the internal circuit between the H and L levels, forexample, depending upon whether it is grounded or not.

This kind of the external input terminal or the control terminal for alogic circuit has a high input impedance. For this reason, the potentialis liable to be varied due to outside noise in a floating state. Inorder to avoid the influence of the outside noise even when thepotential of the external input terminal is in the floating state, inconventional art, an external input terminal 1 is generally connected toa power source voltage Vcc through a pull-up resistor Rpu oralternatively grounded through a pull-down resistor Rpd as illustratedin FIGS. 13A and 13B.

An input buffer 2 having the external input terminal 1 is formed of aninverter circuit made up of a p-channel MOS transistor (abbreviated to“PMOS”) 3 and an n-channel MOS transistor (abbreviated to “NMOS”) 4, forexample, as illustrated in FIGS. 13A and 13B. However, when the externalinput terminal 1 is connected with the pull-up resistor Rpu or thepull-down resistor Rpd, a leakage current sometimes flows into theexternal input terminal 1 using the resistor Rpu or Rpd as a course ofthe current.

For instance, as illustrated in FIG. 14, the leakage current can bereduced by providing a latch circuit 8, which is formed of a NMOStransistor 6 and a PMOS transistor 7 which are gate-controlled by anNMOS transistor 5, to an input node of an input buffer made up oftwo-stage inverter circuits 2 a and 2 b (see Patent Document 1, forexample). When a signal (potential) having the H or L level is given tothe external input terminal 1, the latch circuit 8 carries out a latchoperation according to an output level of the input buffer (two-stageinverter circuits 2 a and 2 b) that operates in response to this signal.By doing this, the latch circuit 8 forcibly fixes the external inputterminal 1 at the H or L level. At the same time, if the external inputterminal 1 is in the floating state (open state), the latch circuit 8turns off the NMOS transistor 5 by using an external signal S, andbrings the NMOS transistor 6 and the PMOS transistor 7 into a conductivestate (hereinafter referred to as “on”) and a non-conductive state(hereinafter referred to as “off”), respectively, by using the pull-upresistor Rpu. In so doing, the latch circuit 8 maintains the externalinput terminal 1 at the H level.

As a similar technology, a bus-hold circuit is known, which is providedfor the purpose of preventing abnormal phenomena including the leakagecurrent and oscillation of a semiconductor device and a data error whichoccur when the external input terminal becomes open (see Patent Document2 and Non-patent Document 1, for example). When the external inputterminal comes into the floating state, the bus-hold circuit maintainsthe preceding logic level given to the external input terminal. Abus-hold circuit of this type is occasionally used as a substitute for apull-up resistor or a pull-down resistor in order to prevent the busfrom coming into an undefined state.

A bus-hold circuit of this type is installed with an overvoltageprotection circuit for blocking the current that flows from an externalinput terminal when the external input terminal of the bus-hold circuitis provided with a signal at a potential higher than the operatingvoltage of the bus-hold circuit (see Patent Document 3, for example).

As a general-purpose logic IC in which the above bus-hold circuit isrealized, the 74 VCX series and the like are available in the market.

Patent Document 1: Unexamined Japanese Patent Publication No. 9-161486

Patent Document 2: U.S. Pat. No. 5,432,462Patent Document 3: U.S. Pat. No. 6,150,845

Non-patent Document 1: “AN-5006J Designing with Bushold”; FairchildSemiconductor Corporation; Application note; First edited March 1999(revised September 1999); page 1-3 DISCLOSURE OF THE INVENTION Problemto be Solved by the Invention

If a latch circuit 8 as shown in Patent Document 1 is installed in aninterface circuit, it is required to ON-OFF control an NMOS transistor 5by using an external signal S depending upon whether an external inputterminal 1 is in a floating state (open state). Therefore, the interfacecircuit needs a special-purpose circuit that determines whether theexternal input terminal 1 is in the floating state (open state) and aspecial-purpose circuit for producing the external signal S to controloperation of the latch circuit 8.

There is the problem of a leakage current in a bus-hold circuit appliedto a multi-drop bus as described in Non-patent Document 1. If a logiclevel of the external input terminal is varied, the bus-hold circuit hasthe problem that electric current consumption is high.

As to a bus-hold circuit installed to prevent a bus from coming into anundefined state, there is concern that input is brought into theundefined state at the rising edge of power supply to the bus-holdcircuit. For this reason, in order to stabilize a potential of the busat the rising edge of power supply, it is necessary to provide, forexample, a pull-up resistor or the like in addition to the bus-holdcircuit.

The present invention has been made in light of the circumstances. It isan object of the invention to provide an interface circuit that iscapable of automatically stabilizing an external input terminal at apredetermined H or L level without using an external signal when theexternal input terminal is in a floating state (open state), has noiseresistance, and is formed in a simple structure in which there is noleakage current from the external input terminal.

Means for Solving Problem

In order to achieve the above object, the interface circuit according tothe invention includes a high-voltage terminal and a low-voltageterminal forming a pair of power source terminals and an external inputterminal, and stabilizes a logic level of the external input terminal atan H level potential (logic high signal) or an L level potential (logiclow signal). The interface circuit is characterized by comprising afirst inverter circuit that is configured with a transistor to invert alogic level of an input signal given to the external input terminal andoutput a logic level that is obtained by inverting the logic level ofthe input signal; a second inverter circuit that is configured with atransistor to generate an output signal having a potential in which thelogic level outputted from the first inverter circuit is inverted, thepotential being higher or lower than a potential of the input signalapplied to the first inverter circuit through the external inputterminal; and a feedback path through which the output signal of thesecond inverter circuit is positive-feedbacked to the external inputterminal.

In other words, the interface circuit according to the inventionbasically has the first inverter circuit that inverts the logic levelhaving the H level potential (logic high signal) or the L levelpotential (logic low signal) which is applied to the external inputterminal, and the second inverter circuit that inverts the logic levelof the output signal of the first inverter circuit, and is so configuredas to positive-feedback the logic level of the output signal of thesecond inverter circuit to an input node (external input terminal) ofthe first inverter circuit.

Especially, a potential of the input signal applied to the input node ofthe first inverter circuit and a potential of the output signaloutputted from an output node of the second inverter circuit arepreviously set so as to satisfy a relationship:

[the potential of the input signal]<[the potential of the output signal]

or

[the potential of the input signal]>[the potential of the outputsignal],

and by positive-feedbacking the output signal of the output node of thesecond inverter circuit to the first input node (external inputterminal), when the external input terminal is in a floating state, thelogic level of the external input terminal is automatically maintainedat the H level potential (logic high signal) or at the L level potential(logic low signal) due to a positive-feedback mechanism. It issufficient if only the potential of the input signal and that of theoutput signal are slightly dissimilar in magnitude.

In the interface circuit thus constructed, when the external inputterminal is in the floating state, an output signal having a potentialhigher or lower than a potential applied to the input node of the firstinverter circuit by the amount corresponding to a predeterminedpotential is positive-feedbacked from the output node of the secondinverter circuit to the input node of the first inverter circuit. As aresult, the potential of the output signal of the second invertercircuit is gradually shifted toward the H or L level potential due tothe positive-feedback mechanism, and is stabilized when reaching the Hor L level potential.

Consequently, in the interface circuit according to the invention, evenif the external input terminal is in the floating state (open state),the potential of the external input terminal is automatically stabilizedat the H or L level potential. In the interface circuit according to theinvention, in any of the cases where the potential of the external inputterminal is automatically stabilized at the H or L level, the potentialof the external input terminal is electrically fixed at the H levelpotential and the potential of the external input terminal iselectrically fixed at the L level potential, the external input terminalis detached away from a high-voltage terminal and a low-voltage terminalby the first and second inverter circuits, so that a leakage currentdoes not occur as in the case where a pull-up or pull-down resistor isused.

In the case where the potential of the external input terminal isautomatically set at the H level potential, the second inverter circuitpreferably includes:

(a) a first transistor that is connected to between the high-voltageterminal and the external input terminal, is in an OFF-state when anoutput signal of the first inverter circuit is at the H level potential,and is an ON-state (conductive state) when the output signal of thefirst inverter circuit is at the L level potential; and(b) second and third transistors serially interposed between thelow-voltage terminal and the external input terminal, wherein at leasteither one of the second and third transistors is in an OFF-state(non-conductive state) when the output signal of the first invertercircuit is at the L level potential, and at least either one of thesecond and third transistors is in the OFF-state when the output signalof the first inverter circuit is at the H level potential, wherein whena potential of the input signal applied to the external input terminalis the H level potential, the second and third transistors output anoutput signal having a potential equal to or higher than the potentialof the input signal, and when the input signal is at a potential otherthan the H level potential, the second and third transistors output anoutput signal having a potential higher than the potential of the inputsignal.

Either one of the second and third transistors may be in the OFF-statewhen the output signal of the first inverter circuit is at the L levelpotential, and the other of the second and third transistors may be inthe OFF-state when the output signal of the first inverter circuit is atthe H level potential. Alternatively, either one or both of the secondand third transistors may be in the OFF-state regardless of whether theoutput signal of the first inverter signal is at the H or L levelpotential. The second and third transistors have a voltage shiftfunction that raises the potential of the output signal of the secondinverter circuit so that the potential of the output signal of thesecond inverter circuit becomes higher than the potential of theexternal input terminal, which is in the floating state, by the amountof a predetermined potential.

If the second inverter circuit is thus constructed, the first invertercircuit preferably has voltage shift means for reducing a potential ofthe output signal of the first inverter circuit with respect to theinput signal having the L level potential which is applied through theexternal input terminal so that the potential of the output signal ofthe first inverter circuit becomes lower than the H level potential tosuch an extent that the first transistor in the second inverter circuitis not turned on. Because of the voltage shift means, the first invertercircuit is capable of increasing a convergence rate toward the H levelpotential in the positive-feedback mechanism.

In the case where the potential of the external input terminal isautomatically set at the L level potential, the second inverter circuitmay preferably includes:

(c) a first transistor that is connected to between the low-voltageterminal and the external input terminal, is in an OFF-state when apotential of an output signal of the first inverter circuit is the Llevel potential, and is in an ON-state when the potential of the outputsignal of the first inverter circuit is the H level potential; and(d) second and third transistors serially interposed between thehigh-voltage terminal and the external input terminal, wherein at leasteither one of the second and third transistors is in an OFF-state whenthe potential of the output signal of the first inverter circuit is theL level potential, and at least either one of the second and thirdtransistors is in the OFF state when the potential of the output signalof the first inverter circuit is the H level potential, wherein when apotential of the input signal applied to the external input terminal isthe L level potential, the second and third transistors output an outputsignal having a potential equal to or lower than the potential of theinput signal, and when the input signal is at a potential other than theL level potential, the second and third transistors output an outputsignal having a potential lower than the potential of the input signal.

Either one of the second and third transistors may be in the OFF-statewhen the output signal of the first inverter circuit is at the H levelpotential, and the other of the second and third transistors may be inthe OFF-state when the output signal of the first inverter circuit is atthe L level potential. Alternatively, either one or both of the secondand third transistors may be in the OFF-state regardless of whether theoutput signal of the first inverter circuit is at the H or L levelpotential. The second and third transistors have a voltage shiftfunction for reducing the potential of the output signal of the secondinverter circuit so that the potential of the output signal of thesecond inverter circuit becomes lower than the potential of the externalinput terminal, which is in the floating state, by the amount of apredetermined potential.

Specifically, if the second inverter circuit is thus constructed, thefirst inverter circuit preferably has voltage shift means for raising apotential of the output signal of the first inverter circuit withrespect to the input signal having the L level potential which isapplied through the external input terminal so that the potential of theoutput signal of the first inverter circuit becomes higher than the Llevel potential to such an extent that the first transistor in thesecond inverter circuit is not turned on.

Preferably, in the interface circuit thus constructed, the secondinverter circuit is constructed so that the potential of the externalinput terminal is automatically set at the H level potential, and theoutput node of the second inverter circuit is provided with currentsupply means for supplying a fixed current in a direction from thehigh-voltage terminal toward the external input terminal. Alternatively,in the case where the second inverter circuit is constructed toautomatically set the potential of the external input terminal at the Llevel potential, it is preferable that the output node of the secondinverter circuit is provided with current supply means for supplying afixed current in a direction from the external input terminal toward thelow-voltage terminal.

The current supply means has an effect that reduces time for theturn-off operation of a MOS transistor and increases the convergencerate toward the H or L level potential in the positive-feedbackmechanism despite a current leakage from the external input terminalwhen the potential of the external input terminal is fixed at the L or Hlevel potential.

Regarding the current supplied to the output node of the second invertercircuit, when the external input terminal comes into the floating state,there simply generates a voltage drop in the MOS transistor that carriesout the voltage shift function of the second inverter circuit, so that aleakage current can be suppressed to be further smaller than a leakagecurrent that occurs when the pull-up or pull-down resistor is used.

Preferably, in the interface circuit, there is provided, for example, aresistor as a current limiting element that is serially interposed inthe feedback path and limits the current flowing through the feedbackpath.

The interface circuit limits the current that flows into the externalinput terminal through the feedback path by using the current limitingelement (for example, resistor) interposed in the feedback path.Therefore, in the interface circuit, the potential of the external inputterminal which is stable at the H level potential can be shifted to theL level potential with a low drive current.

The interface circuit is an interface circuit that is connectable to apower source. The interface circuit comprises an external inputterminal, a first inverter into which a potential of the external inputterminal is inputted, a second inverter into which a potential of anoutput of the first inverter is inputted, and a feedback path throughwhich a potential of an output of the second inverter is feedbacked toan input of the first inverter. The interface circuit is constructed sothat if the feedback path is not provided, the potential of the outputof the second inverter is always virtually higher than the potential ofthe external input terminal within a range where the potential of theexternal input terminal is virtually lower than a potential of a highpotential power line.

Preferably the interface circuit is an interface circuit that isconnectable to a power source, which comprises an external inputterminal, a first inverter into which a potential of the external inputterminal is inputted, a second inverter into which a potential of anoutput of the first inverter is inputted, and a feedback path throughwhich a potential of an output of the second inverter is feedbacked toan input of the first inverter. Preferably, the interface circuit isconstructed so that if the feedback path is not provided, the potentialof the output of the second inverter is always virtually lower than thepotential of the external input terminal within a range where thepotential of the external input terminal is virtually higher than apotential of a low potential power line.

Strictly speaking, the external input terminal of the interface circuitaccording to the invention has a function as a so-called outputterminal, which outputs a predetermined signal having the H or L levelin the floating state. However, the term “external input terminal” willbe consistently used here for convenience.

EFFECT OF THE INVENTION

According to the invention, it is possible to set the potential of theexternal input terminal, which is in the floating state, at the H or Llevel potential, to satisfactorily suppress the leakage current of theexternal input terminal, and to enhance noise resistance by keepingimpedance low with respect to a power source voltage terminal or groundterminal of the external input terminal. Therefore, the interfacecircuit of the invention has a great advantage as an interface circuitfor an external input terminal in various kinds of electronic devices, asemiconductor integrated circuit and the like. Furthermore, since thecircuit itself is simple, the interface circuit of the invention has amerit of being easily installed into a semiconductor integrated circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration view of an interface circuit according toEmbodiment 1 of the invention;

FIG. 2 is a view showing input/output characteristics when positivefeedback from a second inverter circuit to a first inverter circuit inthe interface circuit shown in FIG. 1 is stopped;

FIG. 3 is a configuration view of an interface circuit according toEmbodiment 2 of the invention;

FIG. 4 is a configuration view of an interface circuit according toEmbodiment 3 of the invention;

FIG. 5 is a view showing input/output characteristics when positivefeedback from the second inverter circuit to the first inverter circuitin the interface circuit shown in FIG. 4 is stopped;

FIG. 6 is a configuration view of an interface circuit according toEmbodiment 4 of the invention;

FIG. 7 is a configuration view of an interface circuit according toEmbodiment 5 of the invention;

FIG. 8A is a view showing an example of use in which a PMOS transistoris utilized as a switch;

FIG. 8B is a view showing an example of use of a MOS transistor in whicha gate and a drain of a PMOS transistor are connected to each other toform a p-channel diode;

FIG. 8C is a view showing an example of use of a MOS transistor in whicha gate and a source of a PMOS transistor are connected to each other toform a p-channel resistor;

FIG. 8D is a view showing an example of use in which an NMOS transistoris utilized as a switch;

FIG. 8E is a view showing an example of use of a MOS transistor in whicha gate and a drain of an NMOS transistor are connected to each other toform an n-channel diode;

FIG. 8F is a view showing an example of use of a MOS transistor in whicha gate and a source of an NMOS transistor are connected to each other toform an n-channel resistor;

FIG. 9 is a view showing an example of a configuration of an interfacecircuit, which is used when a configuration example of the secondinverter circuit is verified;

FIG. 10 is a view showing a result of verification of the secondinverter circuit shown in FIG. 9;

FIG. 11 is a view showing another configuration example of the interfacecircuit, which is used when a configuration example of the secondinverter circuit is verified;

FIG. 12 is a view showing a result of verification of the secondinverter circuit shown in FIG. 11;

FIG. 13A is a configuration view showing an example of processing of anexternal input terminal using a pull-up resistor Rpu;

FIG. 13B is a configuration view showing an example of processing of theexternal input terminal using a pull-down resistor Rpd;

FIG. 14 is a view showing an example of a configuration of aconventional interface circuit; and

FIG. 15 is a configuration view of an interface circuit according toEmbodiment 8 of the invention.

BEST MODE OF CARRYING OUT THE INVENTION

An interface circuit according to embodiments of the invention will bedescribed below with reference to the attached drawings.

A high-voltage terminal and a low-voltage terminal which form a pair ofpower source terminals are described as a power source node thatsupplies a positive (plus) power source voltage Vcc and a ground node inwhich a potential is zero, respectively. However, the circuit may be sodesigned that the high-voltage terminal is grounded, and the low-voltageterminal supplies a negative (minus) potential. Alternatively, thecircuit may be so designed as to supply a positive (plus) power sourcevoltage to the high-voltage terminal and a negative (minus) potential tothe low-voltage terminal. In other words, a potential V₁ supplied to thehigh-voltage terminal and a potential V₂ supplied to the low-voltageterminal satisfy a relationship, V₁>V₂.

In this specification, a conductive state and a non-conductive state ofa transistor are referred to as “ON-state” and “OFF-state”,respectively.

Embodiment 1

FIG. 1 shows a configuration of an interface circuit according to afirst embodiment. Illustrated in this drawing is a configuration examplein which a MOS transistor is used as a transistor. To be specific, 10represents a first inverter circuit formed of a PMOS transistor 11 andan NMOS transistor 12, and 20 represents a second inverter circuitformed of two PMOS transistors 21 and 22 and an NMOS transistor 23.

In the first inverter circuit 10, drain electrodes of the PMOStransistor 11 and the NMOS transistor 12 are connected to each other.The first inverter circuit 10 is serially connected to between a powersource node (high-voltage terminal) and a ground node (low-voltageterminal). Gate electrodes of the first inverter circuit 10 areconnected in common to an external input terminal 1 through an inputnode A. The drain electrodes connected to each other are formed as anoutput node B. When receiving a signal having a predetermined potentialat the external input terminal 1, the first inverter circuit 10 turns onand off the PMOS transistor 11 and the NMOS transistor 12 in acomplementary manner. In so doing, the first inverter circuit 10 outputsto the output node B an output signal having a potential in which alogic level of the external input terminal (input node A) is inverted.

To be concrete, when an input signal applied from the external inputterminal 1 to the input node A is at an H level potential, the firstinverter circuit 10 makes the potential of the output node B equal to anL level potential by turning off the PMOS transistor 11 and turning onthe NMOS transistor 12. In contrast, when the potential of the signalapplied from the external input terminal 1 to the input node A is the Llevel potential, the PMOS transistor 11 is turned on, and the NMOStransistor 12 is turned off, thereby making the potential of the outputnode B equal to the H level potential.

In the second inverter circuit 20, two PMOS transistors 21 and 22 whichare serially connected to each other and an NMOS transistor 23 areconnected to between a power source node and a ground node. In thesecond inverter circuit 20, gate electrodes of the transistors 21, 22and 23 are connected in common to form an input node, and connected tothe output node B of the first inverter circuit 10. In the secondinverter circuit 20, a contact point of a drain electrode of the PMOStransistor 21 and a source electrode of the PMOS transistor 22 functionsas an output node C. The output node C is connected to the input node Aof the first inverter circuit 10 to form a feedback path. Outputs of theinverter circuit 20 are positive-feedbacked to the first invertercircuit 10.

Basically, in response to the output signal of the first invertercircuit 10 at the input node (gate electrode), the PMOS transistors 21and 22 and the NMOS transistor 23 forming the second inverter circuit 20are turned on and off in a complementary manner, and have a levelinverting function to provide to the output node C an output signalhaving a potential in which a logic level of the output node B of thefirst inverter circuit 10 is inverted. Especially, the PMOS transistor22 and the NMOS transistor 23 have a voltage shift function that raisesthe potential of the node C by applying the output node C with a signalhaving a predetermined potential which is produced in between the sourceand drain electrodes when the PMOS transistor 22 and the NMOS transistor23 are not in a fully ON-state.

More specifically, when the potential of the external input terminal 1is the H level potential, and the first inverter circuit 10, in responseto this potential, outputs the output signal having the L levelpotential, the PMOS transistors 21 and 22 are turned on, whereas theNMOS transistor 23 is turned off. Since the NMOS transistor 23 is off atthis point, there is no leakage current that occurs through the NMOStransistor 23 in the external input terminal 1.

When the potential of the external input terminal 1 is the L levelpotential, and the first inverter circuit 10, in response to thispotential, outputs the output signal having the H level potential, thePMOS transistors 21 and 22 are turned off, and the NMOS transistor 23 isturned on. Since the PMOS transistor 21 is off at this point, a leakagecurrent that occurs through the PMOS transistor 21 does not occur in theexternal input terminal 1.

If the external input terminal 1 is brought from a grounded state (Llevel) into a floating state (open state), the potentials of the nodes Aand C are not regulated by the external input terminal 1. As a result,the potential of node C is positive-feedbacked to the input node A ofthe first inverter circuit 10 and is increased by degree. The potentialof the output of the first inverter circuit 10 is gradually decreased asthe potential of the node C is increased. In this process, along withthe drop of the potential of the input signal given to the input node ofthe second inverter circuit 20, the PMOS transistors 21 and 22 areturned on. At this time, the NMOS transistor 23 is turned off, and thepotential of the output node C is forcibly fixed at the H levelpotential. Consequently, the potential of the external input terminal 1is stabilized at the H level potential. In other words, if the externalinput terminal 1 is in the floating state (open state), the potential ofthe external input terminal 1 is automatically set at the H levelpotential.

If the output of the second inverter circuit 20 is notpositive-feedbacked to the input node A of the first inverter circuit10, the second inverter circuit 20 per se outputs the output signalhaving a potential that is always higher than the potential applied tothe node A with respect to the potential of the input signal applied tothe external input terminal 1. More concretely, the second invertercircuit 20 outputs the output signal having a potential as illustratedby a characteristic X in FIG. 2. Stated differently, for example, whenthe external input terminal 1 is grounded, and the potential applied tothe node A is not fixed at the L level potential, the potential of thenode A is gradually increased by a signal having a potential higher thanthe potential of the external input terminal 1 which ispositive-feedbacked from the second inverter circuit 20 when thepotential of the output signal of the second inverter circuit 20 ispositive-feedbacked to the input node A of the first inverter circuit10. As a result, the potential of the node A automatically converges toand is stabilized at the H level potential. The potential of the node Ais automatically set at the H level potential when the external inputterminal 1 is in the floating state (open state).

According to the interface circuit thus constructed, when the potentialof the external input terminal 1 is set at the H or L level potential,the input state of the external input terminal 1 can be maintainedstable without generating a leakage current. Especially when theexternal input terminal 1 is in the floating state (open state), thepotential of the external input terminal 1 can be automatically set atthe H level potential, which eliminates the need for a conventionalpull-up resistor Rpu. Moreover, when the potential of the external inputterminal 1 is forcibly fixed at the L level potential, the PMOStransistor 21 is in the OFF-state as mentioned above, so that a leakagecurrent through the external input terminal 1 does not occur.Accordingly, the interface circuit of the invention is capable ofstabilizing the potential of the external input terminal 1 at the H or Llevel potential when various kinds of electronic devices are connectedto the external input terminal 1.

Embodiment 2

The above-mentioned embodiment is so designed that when the externalinput terminal 1 is in the floating state (open state), the potential ofthe external input terminal 1 is automatically set at the H levelpotential. However, the interface circuit according to the invention maybe constructed so that the potential of the external input terminal 1 isautomatically set at the L level potential. FIG. 3 is a configurationview of an interface circuit showing such an embodiment. Parts identicalto those of the interface circuit shown in FIG. 1 are provided with thesame reference numerals.

The interface circuit is configured by connecting the second inverter 20to the output node B of the first inverter circuit 10. In the secondinverter circuit 10, a PMOS transistor 24 and two NMOS transistors 25and 26 are serially connected to between a power source node and aground node, and gate electrodes of the transistors 24, 25 and 26 areconnected in common to form an input node that is connected to theoutput node B of the first inverter circuit 10. A contact point of asource electrode of the NMOS transistor 25 and a drain electrode of theNMOS transistor 26 is an output node C. The output node C is connectedto the input node A of the first inverter circuit 10. In this manner,the output of the second inverter circuit 20 is positive-feedbacked tothe first inverter circuit 10.

Basically, the PMOS transistor 24 and the NMOS transistors 25 and 26forming the second inverter circuit 20 are turned on and off in acomplementary manner in response to the output signal of the firstinverter circuit 10 at the input node (gate electrode). The PMOStransistor 24 and the NMOS transistors 25 and 26 have a level invertingfunction that provides to the output node C a signal at a potential inwhich a logic level of the output node B of the first inverter circuit10 is inverted. Especially the NMOS transistor 25 and the PMOStransistor 24 have a voltage shift function to reduce the potential ofthe node C by applying the output node C with a predetermined voltagedrop caused in between the source and drain electrodes when the NMOStransistor 25 and the PMOS transistor 24 are not in a fully ON-state.

According to the interface circuit thus constructed, when the externalinput terminal 1 is in the floating state (open state), the potentialsof the nodes A and C are not regulated by the external input terminal 1,so that the potential of the node C is positive-feedbacked to the inputnode A of the first inverter circuit 10 and is reduced by degree. Alongwith the drop of the potential, the potential of the output of the firstinverter circuit 10 is gradually increased. The PMOS transistor 24 isturned off due to the rise of the potential of the signal given to theinput node of the second inverter circuit 20. At this time, the NMOStransistors 25 and 26 are turned on, and the potential of the outputnode C is forcibly fixed at the L level. As a result, the potential ofthe external input terminal 1 is stabilized at the L level potential. Inother words, if the external input terminal 1 is in the floating state(open state), the potential of the external input terminal 1 isautomatically set at the L level potential.

The interface circuit thus constructed is capable of maintaining astable state of the potential of the external input terminal 1 withoutcausing a leakage current when the potential of the external inputterminal 1 is set at the H or L level as in the interface circuit shownin FIG. 1. Especially in the above interface circuit, when the externalinput terminal 1 is in the floating state (open state), the potential ofthe external input terminal 1 can be automatically set at the L levelpotential. Therefore, it is not necessary in the interface circuit ofthe invention to connect a pull-down resistor Rpd to reduce thepotential of the external input terminal 1 as in conventional art.Furthermore, when the potential of the external input terminal 1 isforcibly fixed at the H level potential, a leakage current through theexternal input terminal 1 does not occur since the NMOS transistor 26 isin the OFF-state. The interface circuit of the invention has a greatadvantage of stabilizing the potential of the external input terminal 1at the H or L level potential when it is connected to the external inputterminal 1 of various kinds of electronic devices.

Embodiment 3

In the interface circuit according to the invention, it is alsoeffective to incorporate into the first inverter circuit 10 adiode-connected MOS transistor that shifts the potential of the outputsignal outputted from the first inverter circuit 10 to such an extentthat the second inverter circuit 20 is not turned on or off when thepotential applied to the input node A is either the L or H levelpotential. Specifically, for instance, in the case of the interfacecircuit shown in FIG. 1, a diode-connected PMOS transistor 13 isserially connected to between a power source node and a source electrodeof a PMOS transistor 11 as illustrated in FIG. 4, thereby reducing apotential of an output node B by the amount of operation thresholdvoltage of the PMOS transistor 13.

In the interface circuit thus constructed, if the external inputterminal 1 is grounded, the PMOS transistor 11 is turned on, and theNMOS transistor 12 is turned off. A potential of the source electrode ofthe PMOS transistor 11 and the potential of the node B then becomeapproximately equal to each other. At this point, the potential of thenode B is reduced to be lower than voltage Vcc of the power source nodeby the amount of the operation threshold voltage of the PMOS transistor13 since source-drain resistance of the NMOS transistor 12 is largerthan source-drain resistance of the PMOS transistor 13. In addition,potential difference between a gate and a source of the PMOS transistor21 in the second inverter circuit 20 becomes approximately equal topotential difference between a gate and a source of the PMOS transistor13 in the first inverter circuit 10. Therefore, the PMOS transistor 21is turned off. As a result, the interface circuit can maintain thepotential of the external input terminal 1 at the L level potentialwithout causing a leakage current.

In practice, the interface circuit of the invention sometimes causes asmall leakage current due to variation of the operation thresholdvoltage and of transistor size of the PMOS transistor 13 and the PMOStransistor 21. However, this does not diminish the advantage of theinvention.

When the external input terminal 1 is released from the grounded stateand brought into the floating state, the potential of the node A isincreased due to a positive-feedback mechanism from the second invertercircuit 20. Along with the rise of the potential of the node A, apotential of an output signal of the first inverter circuit 10 isreduced, and the potential of the external input terminal 1 isautomatically set at the H level potential as stated above.

When the PMOS transistor 11 is in a ON-state, the PMOS transistor 13 andthe PMOS transistor 21 of the second inverter circuit 20 form anequivalent current mirror circuit. Due to the existence of the PMOStransistor 13 as described above, a potential applied to the gateelectrode of the PMOS transistor 21 (potential of the node B) ismaintained lower than the power source voltage Vcc of the PMOStransistor 21 by the amount of the operation threshold voltage of thePMOS transistor 21. Accordingly the external input terminal 1 comes intothe floating state, and the potential of the external input terminal 1is increased. Consequently, it is possible to shorten time untilreducing a potential of a signal applied to the gate electrode of thePMOS transistor 21 below the operation threshold voltage of the PMOStransistor 21. As a result, the PMOS transistor 21 is instantaneouslyturned on, so that it is possible to drastically reduce the timerequired for the potential of the external input terminal 1 to beshifted from the floating state to the H level potential.

In this case, if the output of the second inverter circuit 20 is notpositive-feedbacked to the input node A of the first inverter circuit10, the potential of the output signal outputted from the secondinverter circuit 20 (potential of the node C) changes, for example, asshown by a characteristic Y of FIG. 5 with respect to the potential ofthe signal applied to the external input terminal 1, thereby becoming apotential that is always larger than the potential applied to the nodeA. For this reason, when the potential of the signal applied to the nodeA is not fixed at the L or H level potential, if the output signal ofthe second inverter circuit 20 is positive-feedbacked to the input nodeA of the first inverter circuit 10, the potential of the output signalof the second inverter circuit 20 quickly becomes the H level potential.

Embodiment 4

In the case of the interface circuit shown in FIG. 3, a diode-connectedNMOS transistor 14 is connected to between the source electrode and theground node of the NMOS transistor 12 as illustrated in FIG. 6, and apotential applied to the gate electrode of the NMOS transistor 26 in thesecond inverter circuit 20 (potential of the node B) is set higher thana ground potential of the NMOS transistor 26 by the amount of theoperation threshold voltage of the NMOS transistor 26.

Since the interface circuit of the invention uses the above NMOStransistor 14, the potential of the external input terminal 1 is shiftedfrom the H level potential to the floating state and is reduced.Accordingly, it is possible to shorten time until raising the potentialapplied to the gate electrode of the NMOS transistor 26 above theoperation threshold voltage of the NMOS transistor 26. As a result, inthe interface circuit of invention, since the NMOS transistor 26 isinstantaneously turned on, it is possible to drastically reduce timerequired for the potential of the external input terminal 1 to beshifted from the floating state to the L level potential.

Embodiment 5

In the interface circuit of the invention, if the potential of theexternal input terminal 1 is set at the H or L level potential by usingthe interface circuit, it is also effective to supply a fixed currentfrom an external power source to the external input terminal 1. That isto say, in the interface circuit illustrated in FIG. 1, when theexternal input terminal 1 comes into the floating state, the powersource voltage Vcc is applied to the external input terminal 1 by thePMOS transistor 21 in the second inverter circuit 20, which increasesthe potential of the external input terminal 1. The PMOS transistor 21has a sufficiently high resistance value during an OFF-state in order toprevent a leakage current caused when the external input terminal 1 isgrounded. Therefore, when the external input terminal 1 is brought fromthe grounded state into the floating state, it sometimes takes long timebefore the potential of the external input terminal 1 is shifted to theH level potential as described above. The resistance value of the PMOStransistor 21 during an OFF-state is changed due to ambient temperature.Accordingly, the time that is required to turn on the PMOS transistor 21and to shift the potential of the external input terminal 1 to the Hlevel potential has a temperature dependency.

Therefore, the interface circuit of the invention may be provided with acurrent mirror circuit 30 as a power source for supplying the fixedcurrent to the external input terminal 1 as illustrated in FIG. 7. Inaddition, it is preferable that the interface circuit of the inventionreduces the time required to turn on the PMOS transistor 21. To bespecific, in the interface circuit of the invention, the current mirrorcircuit 30 of a current-discharge type which is driven by a constantcurrent source 31 is formed of two PMOS transistors 32 and 33. When theexternal input terminal 1 comes into the floating state, the constantcurrent source 31 supplies the fixed current from the current mirrorcircuit 30 to the external input terminal 1.

In the interface circuit provided with the current mirror circuit 30mentioned above, when the external input terminal 1 is grounded, currentflows from the current mirror circuit 30 to the external input terminal1. When the external input terminal 1 is brought into the floatingstate, the potential of the external input terminal 1 is rapidlyincreased due to the current supplied from the current mirror circuit 30in the interface circuit of the invention. As a result, the interfacecircuit of the invention reduces the time required for the PMOStransistor 21 in the second inverter circuit 20 to be turned on.

Therefore, the potential of the external input terminal 1 is quicklyraised to the H level potential. The PMOS transistor 21 is then turnedon, and impedance of the external input terminal 1 with respect to theground node is controlled by impedance of the NMOS transistor 23.Accordingly, most of the current that flows from the current mirrorcircuit 30 to the external input terminal 1 disappears.

Impedance of the external input terminal 1 with respect to the powersource node is controlled by impedance of the PMOS transistor 21. Forthis reason, the current supplied from the current mirror circuit 30 tothe external input terminal 1 can be reduced to be much smaller than theleakage current caused by the conventional pull-up Rpu. As compared tothe interface circuit that is constructed as shown in FIG. 1, workingcurrent is slightly increased in the interface circuit shown in FIG. 7.It is possible, however, to instantaneously shift the potential of theexternal input terminal 1 in the floating state to the H levelpotential. Consequently, the interface circuit of the invention has anadvantage of speeding up the operations in the interface circuit whilereducing the leakage current.

Embodiment 6

The above-described current mirror circuit can also be adapted to aninterface circuit that automatically sets the potential of the externalinput terminal 1 in the floating state at the L level potential.Although details are not illustrated in the drawings, the interfacecircuit shown FIG. 3 can be formed by constructing a current mirrorcircuit of a current-suction type so that a certain amount of current issucked from the external input terminal 1. In the above-describedinterface circuit, time required for the NMOS transistor 26 to be turnedon is reduced, so that the above-described interface circuit has asimilar advantage to the interface circuit shown in FIG. 7.

Embodiment 7

In each of the above embodiment, the second inverter circuit 20 of theinterface circuit of the invention is formed of the two PMOS transistors21 and 22 and the NMOS transistor 23 as an example of automaticallysetting the potential of the external input terminal 1 in the floatingstate at the H level potential. Moreover, as an example of automaticallysetting the potential of the external input terminal 1 in the floatingstate at the L level potential, the second inverter circuit 20 of theinterface circuit of the invention is formed of the PMOS transistor 24and the two NMOS transistors 25 and 26.

However, a basic requirement for the second inverter circuit 20 is toinclude:

(a) a main MOS transistor (level inverting function) that inverts alogic level by being turned on or off according to the potential of theoutput signal outputted from the first inverter circuit 10; and

(b) an auxiliary MOS transistor (voltage shift function) that producesthe output signal having the predetermined potential when the externalinput terminal is in the floating state by being turned off according tothe current flowing through the main MOS transistor or according to thepotential of the output signal outputted from the first inverter circuit10, and shifts the potential of the output signal from the main MOStransistor.

Specifically in the case of the interface circuit that sets thepotential of the external input terminal 1 at the H level potential whenthe external input terminal 1 is in the floating state, the secondinverter circuit 20 needs only include at least one main MOS transistorthat is turned on or off according to the potential of the output signalfrom the first inverter circuit 10 and at least one auxiliary MOStransistor that raises the potential of the output node C so that thepotential of the output node C is higher than the potential applied tothe external input terminal 1.

In the case of the interface circuit that sets the potential of theexternal input terminal 1 at the L level potential when the externalinput terminal 1 is in the floating state, the second inverter circuit20 needs only include at least one main MOS transistor that is turned onor off according to the potential of the output signal outputted fromthe first inverter circuit 10 and at least one auxiliary MOS transistorthat reduces the potential of the output node C so that the potential ofthe output node C is lower than the potential of the signal applied tothe external input terminal 1 when the external input terminal 1 is inthe floating state.

The MOS transistors have functions of a switch, a diode and a resistoras illustrated in FIGS. 8A, 8B, 8C, 8D, 8E and 8F. More specifically,each of the PMOS and the NMOS having a three-terminal structure in whicha gate is used as an input terminal as illustrated in FIGS. 8A and 8Dserves as a switch that turns on/off between the source and drainaccording to the potential of the input terminal. The PMOS and the NMOShaving a two-terminal structure in which a gate and a drain areconnected to each other as illustrated in FIGS. 8B and 8E serve as ap-channel diode (P-D) and an n-channel diode (N-D), respectively.Furthermore, the PMOS and the NMOS having a two-terminal structure inwhich a gate and a source are connected to each other as illustrated inFIGS. 8C and 8F serve as a p-channel resistor (P-R) and an n-channelresistor (N-R), respectively.

A resistance value, an operation threshold voltage and the like of thePMOS and the NMOS having a three-terminal structure in which a gate isused as an input terminal as illustrated in FIGS. 8A and 8D aredetermined by channel widths of these MOS transistors and the like.Accordingly, if it is desired that input/output characteristics of thefirst and second inverter circuits 10 and 20 in the interface circuitwhen the positive feedback is not performed be similar to those shown inFIG. 2 or 5, it is only necessary to select MOS transistors according tosuch a desire, allow at least one of the MOS transistors to be turnedon/off, and provide at least one of the other MOS transistors with alevel shift function that shifts the potential of the output signal.

However, it is also a fact that, the inverter circuits 10 and 20 may notfunction as inverter circuits depending upon the combination of the MOStransistors illustrated in FIG. 8.

The inventors verified what functions were required in MOS transistorsto be employed as second-stage and third-stage MOS transistors if afirst-stage MOS transistor located on the side of the power source nodein the second inverter circuit 20 was the PMOS transistor 21 as shown inFIG. 9 and functioned as a main MOS transistor (first transistor) thatis turned on or off according to the potential of the output signaloutputted from the first inverter circuit 10. This verification wasconducted under the conditions that the transistors forming the firstinverter circuit 10 and the first-stage to third-stage MOS transistorsof the second inverter circuit 20 were all equal in size, and that theexternal input terminal 1 in floating state was at the H levelpotential.

FIG. 10 shows a result of the verification. In FIG. 10, “◯” means thatthe circuit effectively functions as the second inverter circuit 20. “X”means that the circuit does not function as the second inverter circuit20. “Δ” means that the circuit does not function as the second invertercircuit 20 when the first-stage to third-stage MOS transistors are allequal in size, but can be made to function as the second invertercircuit 20 by adjusting the sizes of the first-stage to third-stage MOStransistors.

That is to say, the verification result shown in FIG. 10 indicates thatwhen the first-stage MOS transistor is formed of a PMOS transistor thatcarries out the ON-OFF operation, it is possible to design as the secondinverter 20 if at least either one of the second-stage and third-stageMOS transistors is a P resistor, an N resistor or a three-terminal NMOStransistor, and if at least either one of the second-stage andthird-stage MOS transistors is selected from transistors other than thethree-terminal NMOS transistor.

The inventors also conducted a verification in the same manner as to theconfiguration of the second inverter circuit 20 in the case where thefirst inverter circuit 10 itself was provided with the PMOS transistor13 that shifts the potential of the output signal as illustrated in FIG.11. Consequently, a verification result shown in FIG. 12 was obtained.The verification was conducted under the conditions that the transistorsforming the first inverter circuit 10 and the first-stage to third-stageMOS transistors of the second inverter circuit 20 were all identical incharacteristics, and that the external input terminal 1 in the floatingstate was at the H level potential.

These verifications brought the following result.

(a) By providing a first transistor 21 that is connected to between thepower source node (high-voltage terminal) and the external inputterminal 1, the first transistor 21 being turned off when the potentialof the output signal of the first inverter circuit 10 is the H levelpotential, and turned on when the potential of the output signal of thefirst inverter circuit 10 is the L level potential, and second and thirdtransistors 22 and 23 that are serially interposed between the groundnode (low-voltage terminal) and the external input terminal 1; and

(b) by constructing the second inverter circuit 20 by the second andthird transistors 22 and 23 whose operating conditions are set such thatat least either one of the second and third transistors 22 and 23 isturned off when the potential of the output signal of the first invertercircuit 10 is the L level potential, and at least either one of them isturned off when the potential of the output signal of the first inverter10 is the H level potential,

(c) a potential equal to or higher than the potential of the inputsignal applied to the external input terminal 1 is outputted when thepotential of the input signal is the H level potential, and an outputsignal having a potential higher than the potential of the input signalis outputted when the potential of the input signal is at a potentialother than the H level potential.

Verification results shown in FIGS. 10 and 12 relate to the case inwhich the interface circuits shown in FIGS. 9 and 11 are constructed toraise the potential of the external input terminal 1 in the floatingstate to the H level potential.

Accordingly, criteria for selecting the second-stage and third-stage MOStransistors of the interface circuit that maintains the external inputterminal 1 at the L level potential are as listed below.

(a) Polarities of the ground node and the power source node arereversed.

(b) A transistor to be located on the side of the ground node in thesecond inverter circuit 20 is the first-stage MOS transistor.

(c) Polarities of all MOS transistor channels are reversed.

Embodiment 8

In the interface circuit of the invention, when a signal having the Hlevel potential is inputted to the external input terminal 1 or when theexternal input terminal 1 is in the floating state and is stable at theH level potential, the potential of the external input terminal 1sometimes cannot be shifted from the H level potential to the L levelpotential in a circuit with a low current drive capability. This isbecause the PMOS transistor 21 with low on resistance is used in thesecond inverter circuit 20. In other words, when the external inputterminal 1 is at the H level potential, the PMOS transistor 21 formingthe second inverter circuit 20 is in an ON-state. At this point, thePMOS transistor 21 provides the power source voltage Vcc for driving thePMOS transistor 21 to the external input terminal 1 through the low onresistance of the PMOS transistor 21. For this reason, an elementconnected to the external input terminal 1 is required to have thecurrent drive capability that shifts the potential of the external inputterminal 1 from the H level potential to the L level potential,prevailing against the current flowing from the node C into the externalinput terminal 1.

Therefore, in the interface circuit of the invention, it is preferablethat a current limiting element R is serially interposed in the feedbackpath running between the node C and the node A as illustrated in FIG.15. FIG. 15 is a configuration view of an interface circuit according toEmbodiment 8, and parts identical to those of the interface circuitshown in FIG. 1 are provided with the same reference numerals.

The current limiting element R limits the current flowing from the nodeC into the external input terminal 1 when the potential of the externalinput terminal 1 is shifted from the H level potential to the L levelpotential. Concretely, the current limiting element R may be a resistor,the p-channel resistor (P-R) shown in FIG. 8C or the n-channel resistor(N-R) shown in FIG. 8F.

According to the interface circuit in which the current limiting elementR is serially interposed in the feedback path, when an element fordriving the external input terminal 1 shifts the potential of theexternal input terminal 1 from the H level potential to the L levelpotential, the current limiting element R not only limits the currentflowing from the power source but also acts as a general pull-upresistor. Therefore, in the interface circuit of the invention, even ifthe element having a low current drive capability drives the externalinput terminal 1, it is possible to shift the potential of the externalinput terminal 1 from the H level potential to the L level potentialwithout fail.

In the interface circuit of the invention, although the current limitingelement R is serially interposed in the feedback path, an externalsignal is unnecessary as in the other embodiments, and the potential ofthe external input terminal 1 can be automatically set at the H or Llevel potential while the advantage of preventing a leakage current isretained.

If the interface circuit of the invention is applied especially to abus-hold circuit that is applied to a multidrop bus, the problem of theleakage current is solved, and only a small amount of consumptioncurrent is required even if the logic level of the external inputterminal is changed. In the interface circuit of the invention, sincethe potential of the external input terminal 1 is automatically set atthe H or L level potential, the problem that the external input terminal1 comes into the undefined state at the rising edge can be solved, too.The interface circuit of the invention does not require a pull-upresistor and a pull-down resistor, so that it is possible to reduce chiparea of a semiconductor device.

A general bus-hold circuit is installed with an over voltage protectioncircuit that prevents the current flowing from an external inputterminal of the bus-hold circuit when a signal having a potential higherthan differential voltage is given to the external input terminal.Needless to say, the interface circuit of the invention may be providedwith measures against an over voltage input as in a bus-hold circuitdescribed in Patent Document 3 and the like.

The current limiting element R of Embodiment 8 shown in FIG. 15 has theadvantage of limiting the current flowing from the external inputterminal 1 to the node C. The interface circuit of the invention is veryeffective for the reasons that the current flowing from the externalinput terminal 1 to the node C can be effectively prevented by using ananisotropic resistive element as the current limiting element R, and thelike.

Embodiments 1 to 8 show the configuration examples in which thetransistors used in the interface circuit of the invention are all MOStransistors. If the interface circuit of the invention is incorporatedinto an integrated circuit (LSI) using only MOS transistors astransistors in the circuit, it is possible to have the advantage ofbeing able to avoid complicating a fabrication process of forming thetransistors on a substrate as long as all the transistors in theinterface circuit of the invention are also MOS transistors. However, itis also possible to use MES transistors instead of the MOS transistorsin the interface circuit of the invention. In addition, any transistorsfor the use in an LSI are applicable to the embodiments of theinvention.

As described above, according to the interface circuit of the invention,when the external input terminal 1 is in the floating state, thepotential of the external input terminal 1 can be set at the H or Llevel potential. The interface circuit according to the invention doesnot require a pull-up resistor Rpu and a pull-down resistor Rpd whichare required in conventional art. The interface circuit according to theinvention is capable of setting the potential of the external inputterminal 1 at the H or L level potential (it is previously determinedwhether the potential of the external input terminal 1 is to be set atthe H or L level potential) without providing a control signal on thebasis of a determination as to whether the external input terminal 1 isin the floating state as in the circuit shown in FIG. 14.

The interface circuit according to the invention is capable ofeffectively preventing a leakage current by the highly resistive MOStransistor when the potential of the external input terminal 1 is set atthe H or L level potential. Therefore, the interface circuit accordingto the invention offers great practical advantages as an interfacecircuit for an external input terminal in various kinds of electricaldevices, semiconductor integrated circuits and the like in comparisonwith the cases where the potential of the external input terminal 1 isdetermined by using the pull-up resistor Rpu and the pull-down resistorRpd. Moreover, because of the simple circuit configuration, theinterface circuit according to the invention can be applied to asemiconductor integrated circuit, such as a CPU and a memory, withoutdifficulty. If the interface circuit of the invention is formed into anindependent package, and this package is connected to an external inputterminal/control terminal of an existing digital circuit, a logic levelof the external input terminal/control terminal can be set at either Hor L level.

The invention is not limited to the above-described embodiments. In eachof the embodiments, the second inverter circuit 20 is realized using thethree MOS transistors. However, the invention may be realized by usingtwo or more than three MOS transistors. Or, for instance, thesecond-stage and third-stage MOS transistors formed into thetwo-terminal structure by connecting the gate and the source to eachother may be replaced with one MOS transistor having a two-terminalstructure in which a gate and a source with sufficiently high resistancevalues are connected to each other. Alternatively, the interface circuitof the invention may be devised so that switching operation speed isincreased by making the first-stage MOS transistor with a plurality ofMOS transistors connected in parallel. Furthermore, it is sufficient ifa designer or the like designs the inverter circuit so as to implementthe afore-mentioned operation characteristics while properly employingvarious circuit configurations for realizing the inverter circuit.Various modifications can be made without deviating from the spirit andscope of the invention.

1. An interface circuit including a high-voltage terminal and alow-voltage terminal forming a pair of power source terminals and anexternal input terminal, and stabilizing a logic level of the externalinput terminal at an H or L level potential, the interface circuitcomprising: a first inverter circuit that is configured with atransistor to invert a logic level of an input signal given to theexternal input terminal and output a logic level that is obtained byinverting the logic level of the input signal; a second inverter circuitthat is configured with a transistor to generate an output signal havinga potential in which the logic level outputted from the first invertercircuit is inverted, the potential being higher or lower than apotential of the input signal applied to the first inverter circuitthrough the external input terminal; and a feedback path through whichthe output signal of the second inverter circuit is positive-feedbackedto the external input terminal.
 2. The interface circuit according toclaim 1, wherein: the second inverter circuit includes: a firsttransistor that is connected to between the high-voltage terminal andthe external input terminal, the first transistor being in an OFF-statewhen an output of the first inverter circuit is at the H level, andbeing in an ON-state when the output of the first inverter circuit is atthe L level; and second and third transistors serially interposedbetween the low-voltage terminal and the external input terminal,wherein at least either one of the second and third transistors is in anOFF-state when the output of the first inverter circuit is at the Llevel, and at least either one of the second and third transistors is inthe OFF-state when the output of the first inverter circuit is at the Hlevel, wherein when the potential of the input signal applied to theexternal input terminal is the H level potential, the second and thirdtransistors output a potential equal to or higher than the potential ofthe input signal, and when the potential of the input signal is otherthan the H level potential, the second and third transistors output apotential higher than the potential of the input signal.
 3. Theinterface circuit according to claim 2, wherein: the first invertercircuit further has voltage shift means for reducing a potential of theoutput signal of the first inverter circuit with respect to the inputsignal having the L level which is applied through the external inputterminal so that the potential of the output signal of the firstinverter circuit becomes lower than the H level to such an extent thatthe first transistor in the second inverter circuit is not turned on. 4.The interface circuit according to claim 1, wherein: the second invertercircuit includes: a first transistor that is connected to between thelow-voltage terminal and the external input terminal, the firsttransistor being in an OFF-state when an output of the first invertercircuit is at the L level, and being in an ON-state when the output ofthe first inverter circuit is at the H level; and second and thirdtransistors serially interposed between the high-voltage terminal andthe external input terminal, wherein at least either one of the secondand third transistors is in an OFF-state when the output of the firstinverter circuit is at the L level, and at least either one of thesecond and third transistors is in the OFF-state when the output of thefirst inverter circuit is at the H level, wherein when a potential ofthe input signal applied to the external input terminal is the L levelpotential, the second and third transistors output an output signalhaving a potential equal to or lower than the potential of the inputsignal, and when the potential of the input signal is other than the Llevel potential, the second and third transistors output an outputsignal having a potential lower than the potential of the input signal.5. The interface circuit according to claim 4, wherein: the firstinverter circuit further has voltage shift means for raising a potentialof the output signal of the first inverter circuit with respect to theinput signal having the H level which is applied through the externalinput terminal so that the potential of the output signal of the firstinverter circuit becomes higher than the L level to such an extent thatthe first transistor in the second inverter circuit is not turned on. 6.The interface circuit according to claim 1, further including: currentsupply means for supplying a fixed current in a direction from thehigh-voltage terminal to the external input terminal or from theexternal input terminal to the low-voltage terminal.
 7. The interfacecircuit according to claim 1, further including: a current limitingelement that is serially interposed in the feedback path and limitscurrent flowing through the feedback path.
 8. An interface circuit thatis connectable to a power source, comprising: an external inputterminal; a first inverter into which a potential of the external inputterminal is inputted; a second inverter into which a potential of anoutput of the first inverter is inputted; and a feedback path throughwhich a potential of an output of the second inverter is feedbacked toan input of the first inverter, wherein: if the feedback path is notprovided, the potential of the output of the second inverter is alwaysvirtually higher than the potential of the external input terminalwithin a range where the potential of the external input terminal isvirtually lower than a potential of a high potential power line.
 9. Aninterface circuit that is connectable to a power source, comprising: anexternal input terminal; a first inverter into which a potential of theexternal input terminal is inputted; a second inverter into which apotential of an output of the first inverter is inputted; and a feedbackpath through which a potential of an output of the second inverter isfeedbacked to an input of the first inverter, wherein: if the feedbackpath is not provided, the potential of the output of the second inverteris always virtually lower than the potential of the external inputterminal within a range where the potential of the external inputterminal is virtually higher than a potential of a low potential powerline.
 10. The interface circuit according to claim 2, further including:current supply means for supplying a fixed current in a direction fromthe high-voltage terminal to the external input terminal or from theexternal input terminal to the low-voltage terminal.
 11. The interfacecircuit according to claim 3, further including: current supply meansfor supplying a fixed current in a direction from the high-voltageterminal to the external input terminal or from the external inputterminal to the low-voltage terminal.
 12. The interface circuitaccording to claim 4, further including: current supply means forsupplying a fixed current in a direction from the high-voltage terminalto the external input terminal or from the external input terminal tothe low-voltage terminal.
 13. The interface circuit according to claim5, further including: current supply means for supplying a fixed currentin a direction from the high-voltage terminal to the external inputterminal or from the external input terminal to the low-voltageterminal.
 14. The interface circuit according to claim 2, furtherincluding: a current limiting element that is serially interposed in thefeedback path and limits current flowing through the feedback path. 15.The interface circuit according to claim 3, further including: a currentlimiting element that is serially interposed in the feedback path andlimits current flowing through the feedback path.
 16. The interfacecircuit according to claim 4, further including: a current limitingelement that is serially interposed in the feedback path and limitscurrent flowing through the feedback path.
 17. The interface circuitaccording to claim 5, further including: a current limiting element thatis serially interposed in the feedback path and limits current flowingthrough the feedback path.
 18. The interface circuit according to claim6, further including: a current limiting element that is seriallyinterposed in the feedback path and limits current flowing through thefeedback path.
 19. The interface circuit according to claim 10, furtherincluding: a current limiting element that is serially interposed in thefeedback path and limits current flowing through the feedback path. 20.The interface circuit according to claim 11, further including: acurrent limiting element that is serially interposed in the feedbackpath and limits current flowing through the feedback path.